Timer synchronization || Slave Reset mode
This is the 7th tutorial in the STM32 Timer series, and today we will see how to use the slave Reset mode. This is yet another tutorial covering the timer synchronization and today we will see how to synchronize the timers using the reset mode.
I have already covered the slave trigger mode, where the Update Event (UEV) generated by the master is used to resume the counter of the slave timer. Reset mode also works in the similar manner, except the UEV resets the counter of the slave timer.
First of all let’s take a loo at the clock setup
Here I have configured the external crystal, which is 8 MHz, to provide the clock, such that the system will run at 90 MHz. This is to make sure that both the APB timer clocks have the same speeds and so all the timers will wave the same base clock.
The Timer Config
TIM2 will act as the master timer and TIM3 will be the slave timer. Whenever the master counter, TIM2, will overflow, it will issue an UEV signal which will reset the counter of the TIM3.
- Here I have enabled the PWM on channel 1 for both the timers so that we can see their output.
- Both the timers are clocked by the APB clock, so the base frequency is 90 MHz. This is further reduced by using the ARR.
- TIM2 will run at 90MHz/10000 = 9KHz with the duty cycle of 0.4%
- TIM3 will run at 90MHz/1234 = 73KHz with duty cycle of 24%
- TIM2 is the master timer, so the trigger event selection is set as Update Event (UEV). TIM2 will issue this UEV signal when the counter overflows.
- TIM3 is the slave to the TIM2 and is being used in the RESET Mode. The trigger source is ITR1.
Basically in the RESET MODE, whenever the TIM3 receives the UEV signal from TIM2, the TIM3’s counter resets back to 0. We will see this happening in the working section.
/* USER CODE BEGIN 2 */ HAL_TIM_PWM_Start(&htim2, TIM_CHANNEL_1); HAL_TIM_PWM_Start(&htim3, TIM_CHANNEL_1); /* USER CODE END 2 */
Here in the main function we will simply start the PWM for both the timers.
Below is the PWM signals generated by both the timers.
In the picture above you can see the TIM2 PWM signal have the frequency of 9KHz and the Duty of 0.4%. Similarly TIM3 PWM have the frequency of 73KHz and the Duty of 24%.
This is as per the setup we did for the Timers.
If we analyze the TIM3 PWM signal more closely, it can be seen that the signal remains HIGH for the period of 3.33us. This is always the case except at the point where the TIM2’s counter overflows. This is shown below.
At the point where the TIM2’s counter overflows and generates the UEV, the TIM3’s signal remains high for 4.75us.
Let’s understand what exactly is happening at this point.
- Here you can see the TIM3 counter was counting UP from 0, and in between it received the trigger signal from the TIM2.
- At this point the counter resets back to 0 and again starting counting UP.
- That is why the signal remains HIGH for the additional time.
NOTE:- The above picture assumes the CCR(Pulse) value is set to 4, so the signal remains high till the counter reaches the value 4.
If we measure the time difference between when the UEV was issued and when the TIM3 pulse goes LOW, it will be approximately equal to the pulse width of the signal.