ADXL345 tap detection
As I promised in my previous ADXL345 tutorial, today I am going to write about ADXL345 single and double tap functions. I already covered how to interface ADXL345 with STM32 and read the accelerations in different axes (i.e X, Y and Z), you can check that out by going to https://controllerstech.com/adxl345-accelerometer-using-stm32/. Today we will be covering the TAP functionality of this device.
In order to program the single and double taps, we need to write the following registers:-
- POWER_CTL (0x2D) Register for power saving features
- TAP AXES (0x2A) Register for Axis control for tap/double tap
- THRESH_TAP (0x1D) Register for Tap threshold
- DUR (0x21) Register for Tap duration
- LATENT (0x22) Register for Tap Latency
- WINDOW (0x23) Register for Tap window in order to detect Double tap
- INT_MAP (0x2F) Register for Interrupt mapping control
- INT_ENABLE (0x2E) Register for Interrupt enable control
- INT_SOURCE (0x30) Register for getting interrupt Source
After setting values to all registers, we will read the INT_SOURCE register and this will give us the source of interrupt i.e. whether it’s from single or double tap.
Some Insight into the CODE
These functions are from my previous tutorial and I am going to use these to write and read data to ADXL345.
Write the POWER_CTL register first to wake the ADXL345.
Write the values to TAP AXES Register enabling only the tap detection in Z axis.
Set the TAP THRESHOLD to 2.5g. To do that we need to write 40 (2.5/.0625) to the THRESH_TAP Register. This means that you need at least 2.5g acceleration in Z AXIS in order for the tap to qualify as TAP.
Set the TAP DURATION to .02 sec and to do that we need to write 32 (.02/.000625) to the DUR Register. This value indicates maximum time that an event must be above the THRESH_TAP threshold to qualify as a tap event.
Set the TAP LATENCY to .1 sec, write 80 (.1/.0125) to LATENT Register. This is the wait time from the detection of a tap event
to the start of the time window (defined by the window register) during which a possible second tap event can be detected.
Set the TAP WINDOW to .3 sec by writing 240 (.3/.00125) to WINDOW register. This value representing the amount of time after the expiration of the latency time (determined by the latent register) during which a second valid tap can begin.
Enable the INT1 pin by writing 0 to INT_MAP Register.
Next we will read the INT_SOURCE Register and analyse whether it was a single or double tap
As you can see in the image below, on detection, the single and double tap is being transmitted via UART.
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